Semiconductor device and a method of manufacturing the same

ABSTRACT

A reduction in contaminating impurities in a TFT, and a TFT which is reliable, is obtained in a semiconductor device which uses the TFT. By removing contaminating impurities residing in a film interface of the TFT using a solution containing fluorine, a reliable TFT can be obtained.

This application is a continuation of copending U.S. application Ser.No. 13/608,582 filed Sep. 10, 2012 which is a continuation of U.S.application Ser. No. 13/005,728 filed Jan. 13, 2011 (now U.S. Pat. No.8,274,083 issued Sep. 25, 2012) which is a divisional of U.S.application Ser. No. 12/174,124 filed Jul. 16, 2008 (now U.S. Pat. No.7,871,936 issued Jan. 18, 2011) which is a continuation of U.S.application Ser. No. 09/535,233 filed Mar. 24, 2000 (now U.S. Pat. No.7,402,467 issued Jul. 22, 2008), all of which are incorporated herein byreference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device, such as a thinfilm transistor (TFT), using a crystalline semiconductor film formedover a substrate, and to a method of manufacturing the same. Thesemiconductor device of the present invention includes not only elementssuch as a thin film transistor (TFT) or a MOS transistor, but alsoincludes liquid crystal display devices, EL display devices, EC displaydevices, and image sensors having a semiconductor circuit (such as amicroprocessor, a signal processing circuit, or a high frequencycircuit) structured by these insulating gate type transistors. Inaddition, the semiconductor device of the present invention includeselectronic equipment which is loaded with these display devices, such asa video camera, a digital camera, a projector, a goggle display, a carnavigation system, a personal computer, or a portable informationterminal.

2. Description of the Related Art

At present, thin film transistors (TFT) are used in various kinds ofintegrated circuits as semiconductor elements which use a semiconductorfilm, and in particular are used as switching elements in a pixel regionof an active matrix type liquid crystal display device. In addition, inaccordance with the high mobility of TFTs, they are also used as drivercircuit elements driving the pixel region. It is necessary to use acrystalline semiconductor film, which has a higher mobility than anamorphous semiconductor film, as the semiconductor film used in thedriver circuit. This crystalline semiconductor film is called apolycrystalline semiconductor film, a polysilicon film, or amicrocrystalline semiconductor film.

When evaluating a TFT, the most important characteristic is reliability.Within the problem of reliability, the largest is that an alkaline metal(periodic table group element), a mobile ion, mainly sodium (Na),becomes mixed in. The mixing-in is detected as a phenomenon in which Nais electrified to have a positive electric charge and Vth changes by Namoving as an ion throughout the film, preventing the practical use ofthe TFT. The following can be given as examples of this type of impurityto (hereafter, impurities such as Na which cause the reliability of aTFT to drop are referred to as contaminating impurities throughout thisspecification): alkaline metals (periodic table group 1 elements) andalkaline earth metals (group 2 elements), such as sodium (Na), potassium(K), magnesium (Mg), calcium (Ca), and barium (Ba). The reduction ofthese contaminating impurities is indispensable for the manufacture ofreliable TFTs. However, contaminating impurities get mixed with TFTsfrom a variety of impurity sources, such as gases in the atmosphere orhigh pressure gas cylinders, glass substrates, and manufacturingapparatus such as a sputtering device. In particular, the contaminationfrom a glass substrate is a serious problem, and even by using a glasssubstrate with a Na composition of 0.1% or lower, this reliabilityproblem has not been solved. Therefore, a blocking film such as asilicon nitride film is formed on the substrate, preventingcontaminating impurities contained in the glass substrate fromdiffusing, and preventing a lowering of reliability.

However, as a result of analyzing the contaminating impurityconcentration in a TFT, the contaminating impurity concentration of theinterface between films structuring the TFT is between 5×10¹⁶ atoms/cm³and 5×10¹⁹ atoms/cm³, higher in comparison to the contaminating impurityconcentration within the films (generally 1×10¹⁶ atoms/cm³ or less),identifying the cause of the reduction in TFT reliability. Inparticular, the fact that a contaminating impurity exists in theinterface between a semiconductor film and an insulating film in contactwith the semiconductor film (an insulating film which functions as agate insulating film (hereafter referred to as a gate insulating film),an insulating film which functions as a blocking film, or an interlayerinsulating film), or in the interface between the gate insulating filmand a film which contacts the gate insulating film (such as thesemiconductor film, a gate wiring (this includes a gate electrodethroughout this specification), or an interlayer insulating film), is amajor cause of the harm to TFT reliability.

Note that the impurity concentrations throughout this specification areconcentrations measured by performing an analysis in the depth directionby using secondary ion mass spectroscopy (hereafter referred to asSIMS). A SIMS analysis is a method in which a primary ion is irradiatedonto a test sample, and a mass analysis is performed on secondary ionsemitted from the test sample surface and from a depth of severalangstroms. SIMS analysis is characterized by high detection sensitivityand the ability to analyze microscopic regions. However, an analysisusing SIMS is performed by increasing the current density of the primaryion while sputtering the surface, and therefore there is a limit to theresolution ability in the depth direction. Therefore it is difficult toperform accurate measurements of the element concentration in the filminterface, and SIMS analysis is actually done in succession for a firstfilm and then for a second film in contact with the first film,measuring the element concentration in the interface between the firstfilm and the second film, and in the neighboring area (to severalangstroms). In the present specification, the concentration in theinterface between the first film and the second film, and in theneighboring area (to several angstroms) is taken as the elementconcentration in the interface between the first film and the secondfilm.

An example is shown in FIGS. 4 to 6B in which sodium (Na) exists in theinterface between a gate wiring and a gate insulating film. FIGS. 4 and5 show the result of SIMS analysis of a TFT. A SIMS analysis resultbefore BT processing (bias temperature: heating while applying avoltage) is shown in FIG. 4, and a SIMS analysis result after BTprocessing is shown in FIG. 5. Note that the minimum detection level, orthe background level, of Na in FIGS. 4 and 5 is approximately 1×10¹⁵atoms/cm³.

Only one peak is observed showing the existence of Na in FIG. 4 (beforeBT processing). This is peak A seen in a location corresponding to theinterface between the gate wiring and the gate insulating film, and theneighboring area. However, two peaks are observed showing the existenceof Na after BT processing, as shown in FIG. 5. One of these peaks is thepeak A, also shown in FIG. 4 (before BT processing), seen in thelocation corresponding to the interface between the gate wiring and thegate insulating film, and the neighboring area. The other peak is a peakB seen in a location corresponding to the interface between the gateinsulating film and a semiconductor film, and its neighboring area, andis not seen in FIG. 4 (before BT processing). It is thus understood fromFIGS. 4 and 5 that Na moves within the gate insulating film due to BTprocessing. As a result, changes are seen in the ID-VG characteristicsfrom before BT processing (solid line) to after BT processing (brokenline) for both an n-channel TFT (shown in FIG. 6A) and a p-channel TFT(shown in FIG. 6B). This shows fluctuations in threshold voltage(V_(th)), one of parameters for evaluating TFT characteristic, and itshows a result in which the TFT reliability is harmed.

SUMMARY OF THE INVENTION

An object of the present invention is to lower the concentration of acontaminating impurity not only within a film for forming a TFT, butalso in a film interface, to a level at which it does not have aninfluence on the reliability of a TFT. Another object of the presentinvention is to form a low cost, large screen, high performancesemiconductor device using a TFT with increased reliability.

Note that the above objects of the present invention are objects relatedto a film interface in which the films are not deposited in succession,and are not objects related to a film interface in which the films aredeposited in succession. This is because contaminating impurities arebasically not mixed into an interface between two films when the filmsare deposited in succession, and because the concentration ofcontaminating impurities in the film interface can be made on the sameorder as the low concentration of contaminating impurities within thefilms. However, successive film deposition must be performed using asuccessive film deposition apparatus, and cannot be done easily. Anobject of the present invention is to easily reduce the contaminatingimpurity concentration in a film interface without using a successivefilm deposition apparatus. In addition, an object of the presentinvention is to reduce the contaminating impurity concentration of afilm interface which cannot be formed successively. In practice, if aninsulating film exists on an amorphous semiconductor film,crystallization of the amorphous semiconductor film by annealing isdifficult, and therefore crystallization is performed in a state inwhich there is no insulating film on the semiconductor film. The presentinvention can therefore be applied with the object of reducing thecontaminating impurity concentration in the interface between thesemiconductor film and the insulating film formed in contact with thesemiconductor film. Furthermore, the present invention can be appliedwith the object of reducing the contaminating impurity concentration inthe interface between the insulating film and the gate wiring, for gateinsulating films and gate wirings are generally not formed insuccession.

In order to realize the above objects, the present invention ischaracterized in that after forming a first film, a contaminatingimpurity is removed from the surface of the first film before forming asecond film on the first film, and in that the second film is formed onthe surface of the first film from which the contaminating impurity hasbeen removed as speedily as possible. In other words, the presentinvention is characterized by comprising a step of forming a first film,a step of removing a contaminating impurity from the surface of thefirst film, and a step of forming a second film so as to come in contactwith the first film, from which the contaminating impurity has beenremoved.

An acidic solution containing fluorine is used as an etching solution inthe removal of the contaminating impurity from the surface of the firstfilm in the above constitution, and an extremely thin (5 nm or less)surface of the first film is etched. It is effective to use a means ofspinning the substrate by using a spinning apparatus (spin etcher), andscattering the etching solution contacting the film surface (also calledspin etching or spin etch), as a means of extremely thin etching.

The following can be used as the acidic solution containing fluorine:hydrofluoric acid, dilute hydrofluoric acid, ammonium fluoride, bufferedhydrofluoric acid (a solution mixture of hydrofluoric acid and ammoniumfluoride, hereafter referred to as BHF), FPM (hydrofluoric acid andaqueous hydrogen peroxide), and LAL500 (a solution mixture includingammonium hydrofluoride (NH₄HF₂) at 7.13% and ammonium fluoride (NH₄F) at15.4%), in which the composition of Na is regulated at 0.5 ppb or lower,0.05 ppb or lower in actual analysis. When the contaminating impurity inthe surface of the film is thus removed by using an acidic solutioncontaining fluorine, it is thought that a microscopic amount of fluorineelements remain in the film surface, but no influence imparted to thecharacteristics of the TFT is seen since fluorine is alkaline metal oralkaline earth metal and not a mobile element.

The contaminating impurity concentration in the film interface of asemiconductor device manufactured in accordance with the above structureis within the noise level of the contaminating impurity concentrationwithin the film, and the concentration can be regarded as approximatelythe same as the concentration of the contaminating impurity within thefilm. The sodium concentration within the film can be suppressed byusing a blocking film, as low as to 2×10¹⁶ atoms/cm³ or less in a SIMSanalysis, and, depending upon the conditions, can be reduced below theminimum detection level or less as is currently detected, taking noiseinto account to 1×10¹⁶ atoms/cm³ or less. Thus the contaminatingimpurity concentration in the film interface of a semiconductor devicein accordance with the present invention can be reduced to approximatelythe same as the concentration of the contaminating impurity within thefilm, 2×10¹⁶ atoms/cm³ or less, and depending upon the conditions, itcan be reduced below the minimum detection level or less as is currentlydetected, taking noise into account, to 1×10¹⁶ atoms/cm³ or less. Notethat the above structure shows a case in which the contaminatingimpurity in the surface of the film is removed by an acidic solutioncontaining fluorine, but other acidic solution or organic solvents whichcan remove the contaminating impurity from the film surface can also beused.

Therefore, a semiconductor device of the present invention ischaracterized by having a first film and a second film formed in contactwith the first film, in which the concentration of a contaminatingimpurity in the interface between the first film and the second film is2×10¹⁶ atoms/cm³ or less.

Furthermore, another semiconductor device of the present invention ischaracterized by comprising a first film and a second film formed incontact with the first film, in which the concentration of acontaminating impurity within the first film, the concentration of thecontaminating impurity within the second film, and the concentration ofthe contaminating impurity in the interface between the first film andthe second film is 2×10¹⁶ atoms/cm³ or less.

The above structures can also be characterized in that the first filmand the second film are a crystalline semiconductor film and aninsulating film contacting the crystalline semiconductor film,respectively.

Further, the above structures can also be characterized in that thefirst film and the second film are an insulating film which functions asa gate insulating film and a gate wiring contacting the insulating film,respectively.

An example is shown in FIG. 7 of a SIMS analysis result performed onremoval of a contaminating impurity in the interface between a gateinsulating film and a gate wiring. A peak A showing the existence of Nais observed in the interface between the gate insulating film and thegate wiring of FIG. 7, but it can be understood that the concentrationis considerably low at between 1×10¹⁶ atoms/cm³ and 2×10¹⁶ atoms/cm³.Note that the minimum detection of Na and the background level in FIG. 7are approximately 2×10¹⁴ atoms/cm³.

By using the structure of the present invention, the contaminatingimpurity concentration in the film interface can be reduced, andtherefore the contaminating impurity concentration in SIMS analysis canbe made 2×10¹⁶ atoms/cm³ or less, and, depending upon the conditions,can be made 1×10¹⁶ atoms/cm³ or less, below the minimum detection levelor less as is currently detected, taking noise into account. Therefore,fluctuation in the TFT characteristics can be reduced, and the TFTreliability can be increased.

The contaminating impurity in the structure of the present inventionindicates one element or a multiple number of elements selected fromamong periodic table group 1 elements or group 2 elements. Inparticular, it indicates one element or a multiple number of elementsselected from among Na, K, Mg, Ca, and Ba. Especially, it indicates Na.

Further, the film in the structure of the present invention indicates afilm formed by using all means of formation, such as plasma CVD, thermalCVD, reduced pressure thermal CVD, evaporation, sputtering, thermaloxidation, and anodic oxidation.

In cases where a glass substrate is used as the substrate and the filmsurface is etched by immersing the substrate in an acidic solutioncontaining fluorine (such as hydrofluoric acid, dilute hydrofluoricacid), although slight, the glass substrate will erode, andcontaminating impurities within the glass substrate mix into the acidicsolution, contaminating the acidic solution. If the surface of the filmsstructuring the TFT contacts the contaminated acidic solution, then thisis a source of contamination, and is a problem. Then for cases in whicha glass substrate is used, in the present invention, the etching is notperformed by immersion in the acidic solution, but instead removal ofthe contaminating impurity in the film surface is performed by using ameans of spinning the substrate using a spinning apparatus (spin etcher)and scattering the acidic solution contacting the film surface (alsocalled spin etching, and spin etch). If spin etching is used, thenetching can be performed without the contaminated acidic solutioncontacting the surface of the films structuring the TFT. Note that it isnot always necessary to use spin etching. For example, by using a meansin which the etching solution flows in a constant direction, it ispossible to remove the contaminating impurity in the film surfacewithout contaminating the film surface. Further, by covering the entiretop, bottom, and side surfaces of the glass substrate with a film havingacid resistance, then it is possible to prevent erosion of the substrateby the acidic solution, and it is also possible to prevent the acidicsolution from being contaminated by contaminating impurities within thesubstrate.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIGS. 1A to 1F are diagrams showing a process of manufacturing a TFTaccording to Embodiment 1;

FIGS. 2A to 2E are diagrams showing the process of manufacturing the TFTaccording to Embodiment 1;

FIGS. 3A to 3C are diagrams showing the process of manufacturing the TFTaccording to Embodiment 1;

FIG. 4 is a diagram showing an example of conventional SIMS analysisdata;

FIG. 5 is a diagram showing an example of conventional SIMS analysisdata;

FIGS. 6A and 6B are diagrams showing an example of conventional ID-VGdata;

FIG. 7 is a diagram showing an example of SIMS analysis data;

FIGS. 8A to 8D are diagrams showing a process of manufacturing a TFTaccording to Embodiment 2;

FIGS. 9A to 9D are diagrams showing the process of manufacturing the TFTaccording to 2;

FIG. 10 is a cross sectional diagram showing a CMOS circuit and a pixelregion of Embodiment 3;

FIG. 11 is a top view of the pixel region of Embodiment 3;

FIG. 12 is a perspective view showing an active matrix substrate ofEmbodiment 4;

FIG. 13 is a circuit diagram of the EL panel of Embodiment 5;

FIGS. 14A to 14F are diagrams showing various semiconductor devices inEmbodiment 7;

FIGS. 15A to 15D are diagrams showing various semiconductor devices inEmbodiment 7;

FIGS. 16A to 16C are diagrams showing various semiconductor devices inEmbodiment 7;

FIGS. 17A and 17B are a top view and a cross sectional diagram,respectively of an EL display device of Embodiment 8; and

FIGS. 18A to 18C are diagrams showing the structure of a pixel region ofthe EL display device of Embodiment 9.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The embodiments of the present invention are explained below, but ofcourse the present invention is not limited to these.

Embodiment 1

Embodiment 1 of the present invention is explained by using FIGS. 1A to3C. An n-channel TFT and a p-channel TFT are manufactured on the samesubstrate, and an embodiment in which an inverter circuit, a basic CMOSstructure, is formed is explained here.

Substrates such as a glass substrate, a plastic substrate, and a ceramicsubstrate can be used as a substrate 101. Further, a silicon substrateon whose surface an insulating film such as a silicon oxide film or asilicon nitride film is formed, and a metallic substrate, typicallystainless steel, may also be used. Of course it is also possible to usea quartz substrate.

A base film 102 made from a silicon nitride film, and a base film 103made from a silicon oxide film are then formed on at least the surfaceof the substrate 101 on which the TFTs are formed. The base films areformed by plasma CVD or sputtering, and are formed as blocking films inorder to prevent diffusion of contaminating impurities which are harmfulto the TFTs from the substrate 101 to a semiconductor film. Thereforethe base film 102 made from a silicon nitride film is formed with athickness of 20 to 100 nm, typically 50 nm, and in addition the basefilm 103 made from a silicon oxide film is formed with a thickness of 50to 500 nm, typically between 150 and 200 nm.

Of course the base films may be formed of only one of the base film 102made from a silicon nitride film, and the base film 103 made from asilicon oxide film, or formed of other insulating films such as anitrated silicon oxide film, but considering TFT reliability, atwo-layer structure is used in Embodiment 1.

It is preferable to use, as the semiconductor film formed contacting thebase film 103, an amorphous semiconductor film formed by a filmdeposition method such as plasma CVD, reduced pressure CVD, orsputtering and a crystalline semiconductor film crystallized by a solidstate growth method such as laser crystallization or heat treatment.Further, it is possible to apply a microcrystalline semiconductor filmformed by the above film deposition methods. Semiconductor materialswhich can be applied here include silicon (Si), germanium (Ge), silicongermanium alloy, and silicon carbide, and compound semiconductormaterials such as gallium arsenide can also be used.

An amorphous semiconductor film 150 is formed with a thickness of 10 to100 nm, typically 50 nm. An amorphous semiconductor film, an amorphoussemiconductor film having microcrystals, and a microcrystallinesemiconductor film can be used as the amorphous semiconductor film 150.Hydrogen is contained at a ratio of between 10 and 40 atom % in anamorphous semiconductor film formed by plasma CVD, and therefore it ispreferable to perform a heat treatment process at 400 to 500° C. beforecrystallization, driving hydrogen out from within the film and reducingthe contained hydrogen amount to 5 atom % or less. Further, theamorphous semiconductor film may be formed by other methods such assputtering or evaporation, but sufficient care must be taken so thatalkaline metals such as sodium do not mix into the film. (See FIG. 1A)

Furthermore, it is possible to use the same deposition method for thebase films and the amorphous semiconductor film, and thereforesuccessive formation of the base film 102, the base film 103, and inaddition, the amorphous semiconductor film 150 is desirable. By formingthe next film without exposing the film surface to the atmosphere afterforming each of the respective films, impurity contamination in the filminterfaces can be prevented. As a result, one cause of the developmentof dispersion in TFT characteristics can be eliminated. Note that forcases in which the base films and the semiconductor film are not formedsuccessively, it is good to remove contaminating impurities from thebase film surface before forming the semiconductor film.

A known laser crystallization technique or a known thermalcrystallization technique may be used for a crystallization process ofthe amorphous semiconductor film 150. Further, a crystallinesemiconductor film can be obtained by a thermal crystallizationtechnique using a catalytic element. In addition, if a gettering processis carried out on a crystalline film 151 formed by a thermalcrystallization technique using a catalytic element, and the catalyticelement is removed, then superior TFT characteristics can be obtained.(See FIG. 1B)

When using a laser crystallization technique, a pulse emission type or acontinuous emission type excimer laser, or a solid state laser such as aYAG laser, a YVO₄ laser, a YLF laser, or a YAlO₃ laser is used. If alaser diode excitation method is used for these solid state lasers, thenhigh output, high repeatability frequency can be realized. The secondharmonic (532 nm), the third harmonic (355 nm), and the fourth harmonic(266 nm) of a YAG laser, a YVO₄ laser, a YLF laser, or a YAlO₃ laser canbe used. Roughly speaking, for cases in which laser light with awavelength of 400 nm or greater is irradiated, the inside of thesemiconductor film is heated by the overlap with the light penetrationdepth, and crystallization can occur. On the other hand, withwavelengths of less than 400 nm, heating is carried out from thesemiconductor film surface and crystallization can occur. Whichever isused, crystallization is performed with an appropriate emission pulsenumber and emission energy density.

When using a laser, a method may be used in which the laser lightemitted from a laser emission device is condensed into a linear shape byan optical system and then irradiated to the semiconductor film. Thecrystallization conditions are appropriately selected by the operator,but if an excimer laser is used, the pulse emission frequency is set to30 Hz, and the laser energy density is between 100 and 400 mJ/cm²(typically from 200 to 300 mJ/cm²). Further, if a YAG laser is used,then the second harmonic is used and the pulse emission frequency is setto between 1 and 10 kHz, and the laser energy density may be from 300 to600 mJ/cm² (typically between 350 and 500 mJ/cm²). Laser light which hasbeen condensed into a linear shape with a width of 100 to 1000 μm, forexample 400 μm, is then irradiated on the entire substrate surface, andirradiation is performed with the overlap ratio of the linear shapelaser light between 80 and 98% at this point.

A crystalline semiconductor film 151 formed in accordance with acrystallization process is formed into a first island shapesemiconductor film 105 and a second island shape semiconductor film 104by using a first photo mask to form a resist mask by using a knownpatterning method, and then dry etching. (See FIG. 1C)

Removal of a contaminating impurity 155 existing in the surface of thefirst island shape semiconductor film 105 and in the second island shapesemiconductor film 104 is performed next. The removal of thecontaminating impurity 155 is performed by a scattering means (alsocalled spin etching and spin etch) using a spinner device (spin etcher)to spin the substrate at 600 rpm for 10 seconds, scattering an acidicsolution containing fluorine which is dripped onto the film surface andbrought into contact therewith. A buffered hydrofluoric acid (BHF)solution of hydrofluoric acid and ammonium fluoride at a mixture ratioof 1:50 by volume is used here as the acidic solution containingfluorine. By using spin etching, an extremely thin film can be removed,and contamination of the film surface by contaminated acid solution canbe prevented. Note that appropriate optimal settings for the conditionssuch as rotation rate of the spinner device and spin time may be foundin accordance with the substrate surface area, etching solutionconcentration, and film material. Further, 1:50 BHF is used as theetching solution, but other acid solution containing fluorine such asBHF with a different mixture ratio and FPM can also be used. (See FIG.1D)

A gate insulating film 106 with silicon oxide or silicon nitride as itsprincipal constituent is then formed on the surfaces of the first islandshape semiconductor film 105 and the second island shape semiconductorfilm 104, from which the contaminating impurity 155 has been removed.The gate insulating film 106 is formed by plasma CVD or sputtering, andis formed with a film thickness of 10 to 200 nm, preferably from 50 to150 nm. Note that by forming the gate insulating film promptly afterremoval of the contaminating impurity 155, a low contaminating impurityconcentration in the interface between the gate insulating film 106 andthe semiconductor films 104 and 105 can be maintained, with a value of2×10¹⁶ atoms/cm³ or less. (See FIG. 1E).

Resist masks 107 and 108 are then formed covering channel formingregions of the second island shape semiconductor film 104 and the firstisland shape semiconductor film 105 by using a second photo mask. Aresist mask 109 may also be formed at this point in the region forming awiring.

A second valence electron control impurity region is then formed bydoping an impurity element which imparts n-type conductivity. Impuritieswhich impart conductivity are hereafter referred to as valence electroncontrol impurities in order to differentiate them from contaminatingimpurities throughout this specification. Also, since the impurities aredoped with intent to impart n-type or p-type conductivity, they may bereferred to as doped impurities. Elements such as phosphorous (P),arsenic (As), and antimony (Sb) are known as valence electron controlimpurity elements which impart n-type conductivity into a crystallinesemiconductor material, and the second valence electron control impurityregion is formed herein by performing ion doping using phosphine (PH₃)with phosphorous taken as the valence electron control impurity.Phosphorous is doped through the gate insulating film 106 and into theunderlying semiconductor films by this process, and therefore theacceleration voltage is set high at 80 keV. The concentration ofphosphorous doped into the semiconductor films is preferably in therange of 1×10¹⁶ to 1×10¹⁹ atoms/cm³, and is set to 1×10¹⁸ atoms/cm³here. Thus regions 110 and 111 in which phosphorous has been doped areformed in the semiconductor films. A portion of the second valenceelectron control impurity region formed here functions as an LDD region.(See FIG. 1F)

The resist masks are then removed. A commercially available alkalinepeeling liquid may be used to remove the resist masks, but use of anashing method is effective. An ashing method is a method in which aplasma is formed in an oxide atmosphere and the hardened resist isexposed to the plasma and removed, and it is effective to add watervapor to the atmosphere in addition to oxygen. (See FIG. 2A)

Removal of a contaminating impurity 156 on the surface of the gateinsulating film 106 is performed next. Similar to the contaminatingimpurity removal from the surface of the first island shapesemiconductor film 105 and from the surface of the second island shapesemiconductor film 104, spin etching is performed for the contaminatingimpurity removal using BHF as the acidic solution containing fluorine.An extremely thin film can be removed, and contamination of the filmsurface by contaminated acid solution can be prevented. Other fluorinecontaining acidic solutions such as FPM can also be used here as theetching solution. (See FIG. 2B).

A first conducting film 112 is then formed contacting the gateinsulating film 106, from whose surface the contaminating impurity 156has been removed. The first conducting film 122 is formed using aconductive material which has an element selected from among Ta, Ti, Mo,and W as its principal constituent. The first conducting film 112 isformed with a thickness of 10 to 100 nm, preferably between 150 and 400nm. Note that by forming the first conducting film 112 promptly after isremoval of the contaminating impurity 156, a low contaminating impurityconcentration in the interface between the first conducting film 112 andthe gate insulating film 106 can be maintained, with a value of 2×10¹⁶atoms/cm³ or less. (See FIG. 2C)

In addition, the first conducting film can be formed using compoundmaterials such as WMo, TaN, MoTa, and WSi_(x) (where 2.4<x<2.7).

Conductive materials such as Ta, Ti, Mo, and W have a resistivity whichis high when compared to Al or Cu, but this does not become a problemwith the surface area of the manufactured circuit in the range of 100cm², and these materials can be used.

Resist masks 113 to 116 are formed next using a third photo mask. Theresist mask 113 is a mask for forming a gate electrode of the p-channelTFT, and resist masks 115 and 116 are a mask for forming a gate wiringand a gate bus line of the p-channel TFT. Furthermore, the resist mask114 is formed covering the entire surface of the first island shapesemiconductor layer, and is formed as a mask in order to prevent avalence electron control impurity from being doped in the next process.

Unnecessary portions of the first conducting film are removed by usingdry etching, forming a second gate electrode 117, a gate wiring 119, anda gate bus line 120. An ashing process may also be performed for casesin which some residual remains after etching.

The resist masks 113 to 116 are then left as is, and a process isperformed to dope a valence electron control impurity element whichimparts p-type conductivity into a portion of the second island shapesemiconductor film 104 in which the p-channel TFT is formed, forming athird valence electron control impurity region. Boron (B), aluminum(Al), and gallium (Ga) are known as valence electron control impurityelements which impart p-type conductivity, and boron is doped here asthe inject impurity element by ion doping using diborane (B₂H₆). Theacceleration voltage is also set to 80 keV here, and boron is doped to aconcentration of 2×10²⁰ atoms/cm³. Thus third valence electron controlimpurity regions 121 and 122 are formed with a high concentration ofboron, as shown in FIG. 2D.

After removing the resist masks formed in FIG. 2D, resist masks 123 to125 are formed using a fourth photo mask. The fourth photo mask is usedto form a gate electrode of the n-channel TFT, and a first gateelectrode 126 is formed by dry etching. The first gate electrode 126 isformed at this point so that it overlaps with a portion of the secondvalence electron control impurity regions 110 and 111 through the gateinsulating film when seen from above. (See FIG. 2E)

The resist masks 123 to 125 are then completely removed, after whichresist masks 129 to 131 are formed from a fifth photo mask. The resistmask 130 covers the first gate electrode 126, and is formed so as tooverlap a portion of the second valence electron control impurityregions 110 and 111 when seen from above. The resist mask 130 is fordetermining the amount of offset of the LDD region.

Further, the resist mask 130 may be used here and a portion of the gateinsulating film may be removed, exposing the surface of thesemiconductor film in which a first valence electron control impurityregion is formed. The process of doping a valence electron controlimpurity element which imparts n-type conductivity can thus beeffectively carried out in the next step.

A process of doping a valence electron control impurity element whichimparts n-type conductivity is then performed, forming the first valenceelectron control impurity region. Thus first valence electron controlimpurity regions 132 and 133, which become a source region and a drainregion, are formed. Ion doping is performed here using phosphine (PH₃).The acceleration voltage is set high at 80 keV for this process too inorder to dope phosphorous through the gate insulating film 106 and intothe underlying semiconductor layers. The phosphorous concentration ofthese regions is high when compared to the process of doping the firstvalence electron control impurity which imparts n-type conductivity, andis preferably from 1×10¹⁹ and 1×10²¹ atoms/cm³. It is set to 1×10²⁰atoms/cm³ here. (See FIG. 3A)

First interlayer insulating films 134 and 135 are then formed over thesurface of the gate insulating film 106, the first and second gateelectrodes 126 and 117, the gate wiring 127, and the gate bus line 128.The first interlayer insulating film 134 comprises silicon nitride witha thickness of 50 nm. Further, the first interlayer insulating film 135comprises silicon oxide with a thickness of 950 nm. Note that it ispreferable to perform contaminating impurity removal from the surfacebefore forming the first interlayer insulating films.

The first interlayer insulating film 134 made from the silicon nitrideformed here is necessary in order to perform the subsequent heattreatment process. It is effective in preventing oxidation of thesurfaces of the first and second gate electrodes 126 and 117, the gatewiring 127, and the gate bus line 128.

It is necessary to perform the heat treatment process in order toactivate the valence electron control impurity elements which impartn-type conductivity or p-type conductivity doped at the respectiveconcentrations. This process may be performed by thermal annealing usingan electric heating furnace, by laser annealing using the abovedescribed excimer laser, and by a rapid thermal annealing (RTA) methodusing a halogen lamp. Activation can be achieved at a low substrateheating temperature with laser annealing, but it is difficult toactivate regions hidden under the gate electrodes. Therefore, theactivation process is performed here by using thermal annealing. Theheat treatment process is performed in a nitrogen atmosphere at between300 and 700° C., preferably between 350 and 550° C., and is performedhere at 450° C. for 2 hours.

When using a laser annealing method, a pulse emission type or acontinuous emission type excimer, or a solid state laser such as a YAGlaser, a YVO₄ laser, a YLF laser, or a YAlO₃ laser can be applied. If alaser diode excitation method is used for these solid state lasers, thenhigh output, high repeatability frequency can be realized. The secondharmonic (532 nm), the third harmonic (355 nm), and the fourth harmonic(266 nm) of a YAG laser, a YVO₄ laser, a YLF laser, or a YAlO₃ laser canbe used. Roughly speaking, for cases in which laser light with awavelength of 400 nm or greater is irradiated, the inside of thesemiconductor film is heated by the overlap with the light penetrationdepth, and annealing can be performed. On the other hand, withwavelengths of less than 400 nm, heating is carried out from thesemiconductor film surface, and annealing can occur. Whichever is used,laser annealing is performed with an appropriate number of emissionpulses and emission energy density.

Between 3 and 90% hydrogen may be added to the nitrogen atmosphere inthe heat treatment process. Further, a hydrogenation process may beperformed after heat treatment in a 3 to 100% hydrogen atmosphere at 150to 500° C., preferably between 300 and 450° C., for 2 to 12 hours.Furthermore, hydrogen plasma processing may be preformed at a substratetemperature of 150 to 500° C., preferably from 200 to 450° C. Whicheveris performed, the TFT characteristics can be raised by hydrogencompensating for defects remaining within the semiconductor films andthe interfaces between them.

After next forming resist masks in a predetermined shape using a sixthphoto mask, contact holes reaching the source regions and the drainregions of the respective TFTs are then formed in the first interlayerinsulating films 134 and 135. A second conducting film is then formed,and source electrodes and drain electrodes 136 to 138 are formed bypatterning using a seventh photo mask. Although not shown in thefigures, in Embodiment 1, the second conducting film is used as a threelayer structure of a 100 nm thick Ti film, a 300 nm thick Al film whichcontains Ti, and a 150 nm thick Ti film, formed successively bysputtering.

The p-channel TFT is thus formed in a self aligning manner in the gateelectrode, and the n-channel TFT is formed in a non-self aligning mannerin the gate electrode by the above processes.

A channel forming region 142, first valence electron control impurityregions 145 and 146, and second valence electron control impurityregions 143 and 144 are formed in the n-channel TFT of the CMOS circuit.The second valence electron control impurity regions here are formedwith regions (GOLD regions) 143 a and 144 a, respectively, which overlapthe gate electrode, and with regions (LDD regions) 143 b and 144 b,respectively, which do not overlap the gate electrode. The first valenceelectron control impurity regions 145 and 146 become source regions anddrain regions.

On the other hand, a channel forming region 139 and third valenceelectron control impurity regions 140 and 141 are formed in thep-channel TFT. The third valence electron control impurity regions 140and 141 then become source regions and drain regions. (See FIG. 3B)

Further, FIG. 3C shows a top view of the inverter circuit, and a crosssectional structure of the TFT section taken along the line A-A′, across sectional section of the gate wiring section taken along the lineB-B′, and a cross sectional structure of the gate bus line section takenalong the line C-C′ correspond to those in FIG. 3B. The gate electrode,the gate wiring, and the gate bus line are formed from the firstconducting film in the present invention. Note that a distinction ismade between the gate electrode, the gate wiring, and the gate bus linein Embodiment 1, but there are times when these are taken together asgate wirings.

An example is shown in FIGS. 1A to 3C of a CMOS circuit made from then-channel TFT and the p-channel TFT formed in combination in acomplimentary manner, but the present invention can also be applied to aNMOS circuit using an n-channel TFT, and to a pixel region of a liquidcrystal display device.

The contaminating impurity concentration in the film boundaries can bereduced in Embodiment 1, and therefore the concentration of harmfulcontaminating impurities can be reduced to 2×10¹⁶ atoms/cm³ or less inSIMS analysis, and can be reduced below the minimum detection level orless as is currently detected taking noise into account, or 1×10¹⁶atoms/cm³ or less, depending upon the conditions. Therefore, dispersionin the TFT characteristics can be reduced, and the TFT reliability canbe increased.

In addition, a process of controlling the threshold voltage of the TFTby performing doping of a valence electron control impurity into theamorphous semiconductor film before the crystallization process may beadded in the above Embodiment 1. A process of, for example, forming acontrolling insulating film (100 to 200 nm film thickness) and dopingboron at a concentration in a range at which the threshold voltage canbe controlled (between 1×10¹⁶ and 1×10¹⁷ atoms/cm³ in SIMS analysis),and then removing the controlling insulating film, can be employed asthe process performing threshold voltage control.

Further, an example of performing patterning of the crystallinesemiconductor film after the crystallization process is shown in.Embodiment 1, but there are no limitations placed upon this, andpatterning may be performed, for example, before the crystallizationprocess or before the doping process.

In addition, although a top gate type TFT is shown in Embodiment 1 as anexample, the present invention can also be applied to a bottom gate typeTFT.

Furthermore, removal of the contaminating impurity is performed on thesurfaces of the semiconductor islands and the surface of the gateinsulating film in Embodiment 1, but contaminating impurity removal mayalso be applied to other areas, such as the surfaces of the base filmsor the surfaces of the interlayer insulating films.

Embodiment 2

Embodiment 2 of the present invention is explained using FIGS. 8A to 9D.An embodiment of the formation of a bottom gate type TFT having ann-channel TFT and to a p-channel TFT is explained here.

First, a glass substrate (Corning 1737, softening point 667° C.) isprepared as a substrate 801. A nitrated silicon oxide film 850 is thenformed with a film thickness of 100 to 300 nm as a base film in order toincrease the TFT electrical characteristics by preventing diffusion ofcontaminating impurities from the substrate.

An example is shown here in which the nitrated silicon oxide film isformed on only one face of the substrate, but it is effective to formthe film on both surfaces of the substrate, not only one. By forming thebase film on both substrate surfaces diffusion of contaminatingimpurities such as sodium from the substrate at the time of manufactureof a semiconductor device can be completely blocked. In addition, it iseven more effective to cover all substrate surfaces by the base film.

A gate wiring (including a gate electrode) 802 is then formed with alaminate structure (for brevity, this is not shown in the figures) onthe base film 850. A tantalum nitride film (film thickness 50 nm) and atantalum film (film thickness 250 nm) are laminated by using sputteringin Embodiment 2, and the gate wiring (including a gate electrode) havinga laminate structure is formed using the know patterning technique ofphotolithography. (See FIG. 8A)

Removal of contaminating impurities 860 from the surface of the basefilm 850 and from the surface of the gate wiring 802 is performed next.The removal of the contaminating impurity 860 is performed by ascattering means (also called spin etching and spin etch) using aspinner device (spin etcher) to spin the substrate at 600 rpm for 10seconds, scattering an acidic solution containing fluorine which isdripped onto the film surface and brought into contact therewith. Abuffered hydrofluoric acid (BHF) solution of hydrofluoric acid andammonium fluoride at a mixture ratio of 1:50 by volume is used here asthe acidic solution containing fluorine. By using spin etching, anextremely thin film can be removed, and contamination of the filmsurface by contaminated acid solution can be prevented. Note thatappropriate optimal settings for the conditions such as rotation rate ofthe spinner device and spin time may be found in accordance with thesubstrate surface area, etching solution concentration, and filmmaterial. Further, 1:50 BHF is used as the etching solution, but otheracid solution containing fluorine such as BHF with a different mixtureratio and FPM can also be used. (See FIG. 8B)

After removal of the contaminating impurities from the surface of thesurface of the base film 850 and from the surface of the gate wiring802, a gate insulating film 803 and an amorphous semiconductor film 804are laminated in order without exposure to the atmosphere. Note that byforming the gate insulating film 803 and the amorphous semiconductorfilm 804 promptly after removal of the contaminating impurities 860, alow contaminating impurity concentration in the interface between thegate wiring 802 and the gate insulating film 803 can be maintained, witha value of 2×10¹⁶ atoms/cm³ or less.

The gate insulating film 803 is made into a laminate structure gateinsulating film in Embodiment 2 for reliability considerations, in whicha silicon nitride film 803 a (film thickness 50 nm) and a silicon oxidefilm 803 b (film thickness 125 nm) are laminated by plasma CVD. Atwo-layer insulating film is employed as the gate insulating film inEmbodiment 2, but a single layer structure, or a laminate structure withthree or more layers may also be used. Further, an amorphous siliconfilm is formed by plasma CVD and with a film thickness of 54 nm on thegate insulating film as the amorphous semiconductor film 804 inEmbodiment 2. Note that the films are formed one after another withoutexposure to the atmosphere so that contaminating matter from theatmosphere does not adhere to the interface of both films. Heattreatment is performed next (at 500° C. for 1 hour) in order to reducethe concentration of hydrogen, which impedes semiconductor filmcrystallization, within the amorphous semiconductor film. (See FIG. 8C)

After the state of FIG. 8C is obtained, crystallization (lasercrystallization) of the amorphous semiconductor film 804 is performed byirradiation of infrared light or ultraviolet light (laser annealing),forming a crystalline semiconductor film (a semiconductor filmcontaining crystals) 805. When using ultraviolet light as thecrystallization technique, excimer laser light or the strong lightemitted from an ultraviolet lamp may be used. If infrared light is usedas the crystallization technique. infrared laser light or the stronglight emitted from an infrared lamp may be used. A linear shape beam ofKrF excimer laser light is irradiated in Embodiment 2. Note that theirradiation conditions are: a pulse frequency of 30 Hz; an overlap ratioof 96%; and a laser energy density of 100 to 500 mJ/cm² (typicallybetween 200 and 300 mJ/cm²). In Embodiment 2, 360 mJ/cm² is used. Notealso that the laser crystallization conditions (such as laser lightwavelength, overlap ratio, irradiation strength, pulse width, frequencyof repetition, and time of irradiation) may be appropriately set by theoperator by considering the film thickness of the amorphoussemiconductor film 804 and the substrate temperature. Depending upon thelaser crystallization conditions, there are cases when the semiconductorfilm is melted and then crystallized, and there are cases when thesemiconductor film is not melted, but crystallized in a solid state oran intermediate state between a solid state and a liquid state. Theamorphous semiconductor film 804 is crystallized by this process,forming the crystalline semiconductor film 805. The crystallinesemiconductor film is a polycrystalline silicon film (polysilicon film)in Embodiment 2. Note that a laser crystallization technique is used inEmbodiment 2, but crystallization may also be performed by using athermal crystallization technique which uses a catalytic element.

Further, in manufacturing the crystalline semiconductor film by thelaser crystallization method, a pulse emission type or a continuousemission type excimer laser, or a solid state laser such as a YAG laser,a YVO₄ laser, a YLF laser, or a YAlO₃ laser can be used. If a laserdiode excitation method is used for these solid state lasers, then highoutput, high repeatability frequency can be realized. The secondharmonic (532 nm), the third harmonic (355 nm), and the fourth harmonic(266 nm) of a YAG laser, a YVO₄ laser, a YLF laser, or a YAlO₃ laser canbe used. Roughly speaking, for cases in which laser light with awavelength of 400 nm or greater is irradiated, the inside of thesemiconductor film is heated by the overlap with the light penetrationdepth, and crystallization can occur. On the other hand, withwavelengths of less than 400 nm, heating is carried out from thesemiconductor film surface and crystallization can occur. Whichever isused, crystallization is performed with an appropriate number ofemission pulses and emission energy density.

When using a laser, a method may be used in which the laser lightemitted from a laser emission device is condensed into a linear shapeand then irradiated to the semiconductor film. The crystallizationconditions are appropriately selected by the operator, but if a YAGlaser is used, then the second harmonic is used and the pulse emissionfrequency is set to between 1 and 10 kHz, and the laser energy densitymay be from 300 to 600 mJ/cm² (typically between 350 and 500 mJ/cm²).Laser light which has been condensed into a linear shape with a width of100 to 1000 μm, for example 400 μm, is then irradiated on the entiresubstrate surface, and irradiation is performed with the overlap ratioof the linear shape laser light between 80 and 98% at this point.

Next, a valence electron control impurity element doping process isperformed in the crystalline semiconductor film 805 thus formed. After avalence electron control impurity activation process is performed, heattreatment is performed in a hydrogen atmosphere (at 350° C. for 1 hour),hydrogenating the entire substrate body. Note that hydrogenation isperformed by using heat treatment in Embodiment 2, but hydrogenation mayalso be performed by using a plasma hydrogenation process. Island shapesemiconductor films are formed next by a known patterning technique asan active layer having a desired shape.

A source region 815, a drain region 816, low concentration valenceelectron control impurity regions 817 and 818 in which the valenceelectron control impurity is doped at between 1×10¹⁶ and 1×10¹⁹atoms/cm³, and a channel forming region 819 are thus formed through theabove processes in the n-channel TFT, and a source region 821, a drainregion 822, and a channel forming region 820 are thus formed in thep-channel TFT. The low concentration valence electron control impurityregions 817 and 818 of the n-channel type TFT are each formed here witha region (GOLD region) which overlaps the gate electrode, and with aregion (LDD region) which does not overlap the gate electrode, when seenfrom above. (See FIG. 9A)

Removal of contaminating impurities 861 is carried out from the surfaceof the island shape semiconductor films. Similar to the contaminatingimpurity removal from the surface of the base film 850 and from thesurface of the gate wiring 802, the contaminating impurity 861 isremoved by spin etching using BHF as the acidic to solution containingfluorine. An extremely thin film can be removed, and contamination ofthe film surface by contaminated acid solution can be prevented. Otherfluorine containing acidic solutions such as FPM can also be used hereas the etching solution. (See FIG. 9B)

An interlayer insulating film 823 with a laminate structure of a siliconoxide film with a 100 nm film thickness formed by plasma CVD and asilicon oxide film with a film thickness of 940 nm formed by using TEOSand oxygen (O₂) as raw material gasses, is formed, covering the islandshaped semiconductor films from which the contaminating impurities havebeen removed. Note that by forming the interlayer insulating film 823promptly after removal of the contaminating impurity 861, a lowcontaminating impurity concentration in the interface between the islandshape semiconductor films and the interlayer insulating film 823 can bemaintained, with a value of 2×10¹⁶ atoms/cm³ or less. (See FIG. 9C.)

Contact holes are then formed, source wirings 824 and 826, and drainwirings 825 and 827 are formed, and the state shown in FIG. 9D isobtained. Finally, heat treatment is performed in a hydrogen atmosphere,hydrogenating the entire substrate body, and completing the formation ofthe n-channel TFT and the p-channel TFT. This hydrogenation may beperformed using a plasma hydrogenation process.

Note that the process order may be changed in Embodiment 2, andcrystallization may be performed after patterning of the amorphoussemiconductor film.

Further, doping of the valence electron control impurity into theamorphous semiconductor film may be performed before crystallization,and TFT threshold voltage control may also be performed.

The contaminating impurity concentration in the film interface can bereduced in Embodiment 2, and therefore the concentration of harmfulcontaminating impurities can be reduced to 2×10¹⁶ atoms/cm³ or less inSIMS analysis, and, depending upon the conditions, can be reduced to1×10¹⁶ atoms/cm³ or less, or the minimum detection level or less as iscurrently detected taking noise into account. Therefore, dispersion inthe TFT characteristics can be reduced, and the TFT reliability can beincreased.

Embodiment 3

In Embodiment 3, an example is shown in FIGS. 10 and 11 of a liquidcrystal display device equipped with an n-type TFT and a p-type TFTmanufactured in accordance with Embodiment 1 above. The semiconductordevice of Embodiment 3 is equipped with a circuit in which CMOS circuitsand a pixel region are arranged in a matrix state on the same substrate.

A cross sectional diagram of the semiconductor device of Embodiment 3 isshown in FIG. 10. In consideration of reliability, the TFTs are formedover a base film 1102 formed on a substrate 1101 in Embodiment 3.

The CMOS circuit shown in the left side of FIG. 10 is called an invertercircuit, and is a basic circuit structuring the semiconductor circuit.By combining these types of inverter circuits, a more complex logiccircuit structure can be made.

The p-channel TFT of the CMOS circuit is formed with a channel formingregion 1154, and third valence electron control impurity regions 1155and 1156. Boron is doped at a concentration of 2×10²⁰ atoms/cm³ into thethird valence electron control impurity regions 1155 and 1156.

On the other hand, the n-channel TFT of the CMOS circuit is formed witha channel forming region 1157, first valence electron control impurityregions 1160 and 1161 into which phosphorous is doped at a concentrationof 1×10¹⁹ to 1×10²¹ atoms/cm³, and second valence electron controlimpurity regions 1158 and 1159. The second valence electron controlimpurity regions 1158 and 1159 are formed with regions (GOLD regions)1158 a and 1159 a, respectively, which overlap a gate electrode 1131,and regions (LDD regions) 1158 b and 1159 b, respectively, which do notoverlap the gate electrode 1131.

The n-channel TFT formed in the pixel region is formed with channelforming regions 1162 and 1163, first valence electron control impurityregions 1168, 1169, and 1145, second valence electron control impurityregions 1164 to 1167, and offset regions 1180 to 1183. The first valenceelectron control impurity regions are regions doped with phosphorous ata concentration of 1×10¹⁹ to 1×10²¹ atoms/cm³, and the second valenceelectron control impurity regions are low concentration regions in whichthe valence electron control impurity concentration is lower than thatof the first valence electron control impurity regions. Phosphorous isdoped into the second valence electron control impurity regions at aconcentration of 1×10¹⁶ to 1×10¹⁹ atoms/cm³. A multi-gate structure isemployed in the pixel region in order to reduce dispersion in the offcurrent, and an offset structure is employed in order to reduce the leakcurrent. The structure is therefore one in which the second valenceelectron control impurity regions do not overlap the gate electrode. Inthe drain side, a low concentration valence electron control impurityregion 1170, a gate insulating film 1160, and a storage capacitorelectrode 1171 doped with a valence electron control impurity elementwhich imparts n-type conductivity at the same concentration as in thesecond valence electron control impurity regions are formed, and astorage capacitor formed in the pixel region is formed.

First interlayer insulating films 1147 (a silicon nitride film with athickness of 50 nm) and 1148 (a silicon oxide film with a thickness of950 nm), source electrodes 1149 to 1151, drain electrodes 1152 and 1153,a passivation film 1401 (a silicon nitride film with a thickness of 50nm), a second interlayer insulating film 1402 (an organic resin filmwith a thickness of 1000 nm), a third interlayer insulating film 1404,and a pixel electrode 1405 (an indium tin oxide (ITO) film with athickness of 100 nm) are then formed.

Materials such as polyimide, acrylic, and polyimide amine can be used asthe organic resin film used in the second interlayer insulating film1402. The following can be given as the advantages of using an organicresin film: simple deposition method; the reduced parasitic capacitybecause the specific dielectric constant is low; and superior levelness.Note that organic resin films other than those stated above can also beused. A polyimide which is thermally polymerized after application tothe substrate is used here.

FIG. 11 is a top view of the pixel region, and is a top view ofapproximately one pixel. N-channel TFTs are formed in the pixel region.A gate electrode 1702 formed successively with a gate wiring 1703intersects, through a gate insulating film not shown in the figures,with a semiconductor layer 1701 below the gate insulating film. A sourceregion, a drain region, and a first valence electron control impurityregion are formed in the semiconductor layer, although not shown in thefigures. Further, a storage capacitor 1707 is formed in the drain sideof the pixel TFT from the semiconductor layer, the gate insulating film,and an electrode made from the same material as the gate electrode.Furthermore, the cross sectional structures shown in FIG. 11 taken alongthe lines A-A′ and B-B′ correspond to those in the cross sectionaldiagram of the pixel region shown in FIG. 10.

A double gate structure is used for the pixel TFT in Embodiment 3, but asingle gate structure may also be used in order to increase the apertureratio, and a multi-gate structure such as a triple gate structure mayalso be used in order to reduce dispersions in the off current. Thestructure of the active matrix substrate of Embodiment 3 is not limitedon the structure shown in Embodiment 3. The structure of the presentinvention is characterized by a gate electrode structure, and a sourceregion, a drain region, and other valence electron control impurityregions formed in a semiconductor layer formed through a gate insulatingfilm. Other structure may be suitably determined by the operator.

Furthermore, a transmission type LCD is manufactured as one example inEmbodiment 3, but there are no limitations placed on this. For example,it is possible to manufacture a reflective type LCD by using a metallicmaterial having reflecting characteristics as the pixel electrodematerial, and then by suitably changing the pixel electrode patterningor adding/eliminating some of the processing steps.

Note that the manufacture method of Embodiment 1 is employed inEmbodiment 3, and therefore the contaminating impurity concentration (Naconcentration) in the interface between the semiconductor film and thegate insulating film 1160, and in the interfaces between the gateinsulating film 1160, the gate electrode, the gate wiring, the gate busline, and the storage capacitor electrodes can be reduced. Thecontaminating impurity concentration in each of the film interfaces canbe reduced to 2×10¹⁶ atoms/cm³ or less in SIMS analysis, and dependingupon the conditions, can be reduced to 1×10¹⁶ atoms/cm³ or less, or theminimum detection level or less as is currently detected taking noiseinto account. Note that by combining the manufacture method ofEmbodiment 2, the contaminating impurity removal process can be appliedto other film interfaces in which it is necessary to reduce thecontaminating impurity concentration. Dispersion in the TFTcharacteristics can be reduced, and the TFT reliability can beincreased, in Embodiment 3.

Embodiment 4

In Embodiment 4, an example of a liquid crystal display devicemanufactured in accordance with the present invention is shown in FIG.12. Known pixel TFT (pixel switching element) manufacturing methods andknown means of cell assembling may be used, so a detailed explanation ofthose areas is omitted.

FIG. 12 is a schematic diagram of an active matrix type liquid crystalpanel of Embodiment 4. As shown in FIG. 12, an active matrix substrateand an opposing substrate face each other, and a liquid crystal issandwiched between the substrates. The active matrix substrate has apixel region 1001, a scanning line driver circuit 1002, and a signalline driver circuit 1003 formed over a glass substrate 1000.

The scanning line driver circuit 1002 and the signal line driver circuit1003 are connected to the pixel region 1001 by a scanning line 1030 anda signal line 1040, respectively. The driver circuits 1002 and 1003 aremainly structured by CMOS circuits.

The scanning line 1030 is formed for each row of the pixel region 1001,and the signal line 1040 is formed for each column. A pixel TFT 810 isformed near the intersection of the scanning line 1030 and the signalline 1040. Agate electrode of a pixel TFT 1010 is connected to thescanning line 1030, and a source thereof is connected to the signal line1040. In addition, a pixel electrode 1060 and a storage capacitor 1070are connected to a drain of the gate electrode.

An opposing substrate 1080 is a glass substrate in which a transparentconductive film such as an ITO film is formed over the entire surface.The transparent conductive film is an opposing electrode for the pixelelectrode 1060 of the pixel region 1001, and drives the liquid crystalmaterial in accordance with an electric field formed between the pixelelectrode and the opposing electrode. If necessary, an orientation film,a black matrix, and a color filter are formed in the opposing substrate1080.

IC chips 1032 and 1033 are attached on the face of the glass substrateof the active matrix substrate side in which an FPC 1031 is attached.The IC chips 1032 and 1033 are structured by forming circuits such as avideo signal process circuit, a timing pulse generator circuit, a γcompensation circuit, a memory circuit, or an arithmetic circuit on asilicon substrate.

Further, liquid crystal display devices which can be manufactured usingthe present invention can be either transmitting type or reflectingtype. The operator may freely select which type. It is thus possible toapply the present invention for all kinds of active matrix typeelectrooptical device (semiconductor device).

Note that in manufacturing the semiconductor device shown in Embodiment4, the constitutions of Embodiments 1 to 3 may be employed, and that itis possible to freely combine the Embodiments.

Embodiment 5

It is possible to apply the present invention to an active matrix typeEL display device. An example is shown in FIG. 13.

FIG. 13 is a circuit diagram of an active matrix type EL display device.Reference numeral 81 denotes a display region, and an x-directionperipheral driver circuit 82 and a y-direction peripheral driver circuit83 are formed in the periphery of the display region 81. Further, eachpixel of the display region 81 has a switching TFT 84, a capacitor 85, acurrent control TFT 86, and an organic EL element 87. An x-directionsignal line 88 a (or 88 b) and a y-direction signal line 80 a (or 80 bor 80 c) are connected to the switching TFT 84. In addition, powersource lines 89 a and 89 b are connected to the current control TFT 86.

Note that the constitution of any of Embodiments 1 to 3 may be combinedwith the active matrix type EL display device of Embodiment 5.

Embodiment 6

It is possible to apply the present invention to all general conventionIC technology. In other words, the present invention can be applied toall semiconductor circuits currently distributed in the marketplace. Forexample, the present invention may be applied to microprocessors such asa RISC processor or an ASIC processor integrated on one chip, and it maybe applied to signal processing circuits, typically liquid crystaldriver circuits (such as a D/A converter, a γ compensation circuit, or asignal divider circuit), and to high frequency circuits used in portableequipment (such as a mobile telephone, a PHS, or a mobile computer).

Furthermore, semiconductor circuits such as a microprocessor are loadedinto many kinds of electronic equipment, and function as the nervecenter circuit. Personal computers, portable information terminals, andall household appliances can be given as typical electronic equipment.Further, computers for controlling an vehicle (such as an automobile ortrain) can also be given. It is possible to apply the present inventionto semiconductor devices such as these.

Embodiment 7

A CMOS circuit and a pixel matrix circuit formed through carrying outthe present invention may be applied to various electrooptical devices(active matrix type liquid crystal displays, active matrix type ELdisplays, active matrix type EC displays). Namely, the present inventionmay be embodied in all the electronic equipments that incorporate thoseelectrooptical devices into display units.

As such an electronic equipment, a video camera, a digital camera, aprojector (rear-type or front-type projector), a head mount display(goggle-type display), a navigation system for vehicles, a stereo forvehicles, a personal computer, and a portable information terminal (amobile computer, a cellular phone, or an electronic book, etc.) may beenumerated. Examples of those are shown in FIGS. 14A to 16C.

FIG. 14A shows a personal computer comprising a main body 2001, an imageinputting unit 2002, a display unit 2003, and a key board 2004 and thelike. The present invention is, applicable to the image inputting unit2002, the display unit 2003, and other signal control circuits.

FIG. 14B shows a video camera comprising a main body 2101, a displayunit 2102, a voice input unit 2103, operation switches 2104, a battery2105, and an image receiving unit 2106 and the like. The presentinvention is applicable to the display unit 2102 and other signalcontrol circuits.

FIG. 14C shows a mobile computer comprising a main body 2201, a cameraunit 2202, an image receiving unit 2203, an operation switch 2204, and adisplay unit 2205 and the like. The present invention is applicable tothe display unit 2205 and other signal control circuits.

FIG. 14D shows a goggle-type display comprising a main body 2301, adisplay unit 2302 and arm portions 2303 and the like. The presentinvention is applicable to the display unit 2302 and other signalcontrol circuits.

FIG. 14E shows a player that employs a recoding medium in which programsare recorded (hereinafter referred to as recording medium), andcomprises a main body 2401, a display unit 2402, a speaker unit 2403, arecording medium 2404, and an operation switch 2405 and the like.Incidentally, this player uses as the recoding medium a DVD (digitalversatile disc), a CD and the like to serve as a tool for enjoying musicor movies, for playing video games and for connecting to the Internet.The present invention is applicable to the display unit 2402 and othersignal control circuits.

FIG. 14F shows a digital camera comprising a main body 2501, a displayunit 2502, an eye piece section 2503, operation switches 2504, and animage receiving unit (not shown) and the like. The present invention isapplicable to the display unit 2502 and other signal control circuits.

FIG. 15A shows a front-type projector comprising a projection device2601, a screen 2602 and the like. The present invention is applicable toa liquid crystal display device 2808 that constitutes a part of theprojection device 2601 and other signal control circuits.

FIG. 15B shows a rear-type projector comprising a main body 2701, aprojection device 2702, a mirror 2703, and a screen 2704 and the like.The present invention is applicable to the liquid crystal display device2808 that constitutes a part of the projection device 2702 and othersignal control circuits.

FIG. 15C is a diagram showing an example of the structure of theprojection devices 2601 and 2702 in FIGS. 15A and 15B. The projectiondevice 2601 or 2702 comprises a light source optical system 2801,mirrors 2802 and 2804 to 2806, dichroic mirrors 2803, a prism 2807,liquid crystal display devices 2808, phase difference plates 2809, and aprojection optical system 2810. The projection optical system 2810consists of an optical system including a projection lens. Thisembodiment shows an example of “three plate type”, but not particularlylimited thereto. For instance, the invention may be applied also to“single plate type”. Further, in the light path indicated by an arrow inFIG. 15C, an optical system such as an optical lens, a film having apolarization function, a film for adjusting a phase difference and an IRfilm may be provided on discretion of a person who carries out theinvention.

FIG. 15D is a diagram showing an example of the structure of the lightsource optical system 2801 in FIG. 15C. In this embodiment, the lightsource optical system 2801 comprises a reflector 2811, light source2812, lens arrays 2813 and 2814, a polarization conversion element 2815,and a condenser lens 2816. The light source optical system shown in FIG.15D is an example thereof, and is not particularly limited. Forinstance, on discretion of a person who carries out the invention, thelight source optical system may be provided with an optical system suchas an optical lens, a film having a polarization function, a film foradjusting the phase difference and an IR film.

The projector shown in FIG. 15 shows the case in which theelectrooptical device of transmission type is employed and anapplication example using the electrooptical device of reflective typeand the EL display device is not illustrated.

FIG. 16A is a cellular phone that is composed of a main body 2901, avoice output unit 2902, a voice input unit 2903, a display unit 2904,operation switches 2905, and an antenna 2906 and the like. The presentinvention can be applied to the voice output unit 2902, the voice inputunit 2903 and the display unit 2904 and other signal control circuits.

FIG. 16B shows a portable book (electronic book) that is comprised of amain body 3001, display units 3002 and 3003, a memory medium 3004, anoperation switch 3005 and an antenna 3006 and the like. The presentinvention can be applied to the display units 3002 and 3003 and othersignal circuits.

FIG. 16C shows a display that is comprised of a main body 3101, asupport base 3102 and a display unit 3103 and the like. The presentinvention can be applied to the display unit 3103. The display accordingto the present invention is advantageous in the case where the displayis particularly large-sized and in the case where the display is 10inches or more in an opposite angle (particularly 30 inches or more).

As described above, the present invention has so wide application rangethat it is applicable to electronic equipments in any field. Inaddition, the electronic equipments of this embodiment may be realizedwith any construction obtained by combining Embodiments 1 through 6.

Embodiment 8

An explanation of an example of the manufacture of an active matrix typeEL (electro-luminescence) display device using the present invention isgiven in Embodiment 8. FIG. 17A is a top view of an EL display deviceusing the present invention, and FIG. 17B is its cross sectionaldiagram.

In FIG. 17A reference numeral 4001 denotes a substrate, 4002 denotes apixel region, 4003 denotes a source side driver circuit, and 4004denotes a gate side driver circuit. Each of the drive circuits is leadto an FPC (flexible printed circuit) 4006 through a wiring 4005, andthus connected to external equipment.

A first sealing material 4101, a covering material 4102, a fillingmaterial 4103, and a second sealing material 4104 are formed at thispoint, surrounding the pixel region 4002, the source side driver circuit4003, and the gate side driver circuit 4004.

In addition, FIG. 17B corresponds to the cross sectional structure ofthe EL display device of FIG. 17A cut along the line A-A′. A driver TFT(however, a CMOS circuit combining an n-channel type TFT and a p-channeltype TFT is shown here) 4201 contained in the source side driver circuit4003, and a pixel TFT (however, a TFT for controlling the current to anEL element is shown here) 4202 contained in the pixel region 4002, areformed over the substrate 4001.

A TFT with the same structure as the CMOS circuit of FIG. 10 is used inEmbodiment 8 in the driver TFT 4201. Further, a TFT with the samestructure as the pixel region of FIG. 10 is used in the pixel TFT 4202.

An interlayer insulating film (planarizing film) 4301 comprises resinmaterial on the driver TFT 4201 and on the pixel TFT 4202, and a pixelelectrode (cathode) 4302 for electrically connecting to the drain of thepixel 114T 4202 is formed on top. A conductive film having lightshielding characteristics (typically a conductive film having aluminum,copper, or silver as its principal constituent, or a laminate film ofthese films) can be used as the pixel electrode 4302. An aluminum alloyis used as the pixel electrode in Embodiment 8.

An insulating film 4303 is then formed on the pixel electrode 4302, andan open section is formed in the insulating film 4303 over the pixelelectrode 4302. An EL (electroluminescence) layer 4304 is formed on thepixel electrode 4302 in the open section. Known organic EL materials orinorganic EL materials can be used as the EL layer 4304. Further, lowmolecular weight materials (monomers) and high molecular weightmaterials (polymers) exist as organic EL materials, and either may beused.

A known technique may be used as the formation method of the EL layer4304. Further, the structure of the EL layer may be a single layerstructure, or a laminate structure of the following freely combined:hole injection layer, hole transport layer, light emitting layer,electron transport layer, electron injection layer.

An anode 4305 is formed from a transparent conductive film on the ELlayer 4304. A compound material of indium oxide and tin oxide, or acompound material of indium oxide and zinc oxide can be used as thetransparent conductive film. It is preferable to remove as much aspossible of the moisture and oxygen existing in the interface betweenthe anode 4305 and the EL layer 4304. Therefore, it is necessary to formthe EL layer 4304 and the anode 4305 inside a vacuum by successive filmdeposition, or to form the EL layer 4304 in a nitrogen or rare gasatmosphere and then form the anode 4305 without exposure to oxygen andmoisture. It is possible to perform the above film deposition inEmbodiment 8 by using a multi-chamber system (cluster tool system) filmdeposition device.

In a region denoted by reference numeral 4306, the anode 4305 iselectrically connected to the wiring 4005. The wiring 4005 is a wiringto impart a given voltage to the anode 4305, and is electricallyconnected to the FPC 4006 through a conductive material 4307.

The EL element made up of the pixel electrode (cathode) 4302, the ELlayer 4304, and the anode 4305 is thus formed as above. The EL elementis surrounded by the covering material 4102 attached to the substrate4001 by the first sealing material 4101 and the second sealing material4104, and is then sealed up by the filling material 4103.

A glass plate, an FRP (fiberglass-reinforced plastic) plate, a PVF(polyvinyl fluoride) film, a Mylar film, a polyester film, and anacrylic film can be used as the covering material 4102. In the case ofEmbodiment 8, the light emission direction from the EL element is towardthe covering material 4102, and therefore a material with lighttransmitting characteristics is used.

However, it is not necessary to use a material with light transmittingcharacteristics for cases in which the light emission direction from theEL element is in the opposite direction from the covering material. Ametallic plate (typically a stainless steel plate), a ceramic plate, ora sheet having a structure in which an aluminum foil is sandwiched byPVF films or Mylar films can be used.

An ultraviolet cured resin or a thermally curable resin can be used asthe filling material 4103, and PVC (polyvinyl chloride), acrylic,polyimide, epoxy resin, silicon resin, PVB (polyvinyl butyral), or EVA(ethylene vinyl acetate) can be used. If a substance absorbing moisture(preferably barium oxide) is placed on the inside of the fillingmaterial 4103, then degradation of the EL element may be suppressed, andthis is preferable. Note that a transparent material is used inEmbodiment 8 so that light from the EL element can pass through thefilling material 4103.

Further, spacers may be included within the filling material 4103. Thespacers may be formed from barium oxide, giving the spacers themselvesthe ability to absorb moisture. Furthermore, when spacers are formed, aresin film formed on the anode 4305 is effective as a buffer layer inrelieving pressure from the spacers.

The wiring 4005 is electrically connected to the FPC 4006 through theconductive material 4307. The wiring 4005 transmits the signals sentfrom the pixel region 4002, from the source side driver circuit 4003,and from the gate side driver circuit 4004 to the FPC 4006, and anelectrical connection to external equipment is provided by the FPC 4006.

Further, the second sealing material 4104 is formed to cover the exposedportion of the first sealing material 4101 and a portion of the FPC 4006in Embodiment 8, a structure which thoroughly shields the EL elementfrom the atmosphere. Thus the EL display device with the cross sectionalstructure of FIG. 17B is formed. Note that the EL display device ofEmbodiment 8 may be manufactured by using a combination of theconstitutions of any of Embodiments 1 to 7.

Embodiment 9

In Embodiment 9, examples of pixel structures are shown in FIG. 18A to18C which can be used in the pixel region of the EL display device shownin Embodiment 8. Note that reference numeral 4401 denotes a sourcewiring of a switching TFT 4402, reference numeral 4403 denotes gatewirings of the switching TFT 4402, reference numeral 4404 denotes acurrent control TFT, 4405 denotes a capacitor, 4406 and 4408 denotecurrent supply lines, and 4407 denotes an EL element.

FIG. 18A is an example of a case with the current supply line 4406common between two pixels. In other words, this is characterized by twopixels being formed with linear symmetry around the current supply line4408. In this case, the number of current supply lines can be reduced,and therefore the pixel region can be made even higher definition.

In addition, FIG. 18B is an example of a case with the current supplyline 4408 formed parallel to the gate wirings 4403. Note that thestructure of FIG. 18B is one in which the current supply line 4408 isformed so as not to overlap with the gate wirings 4403, but if bothwirings are formed on different layers, then they can be formedoverlapping through an insulating film. In this case, the areaexclusively possessed by the current supply line 4408 and the gatewirings 4403 can be shared, and therefore the pixel region can be madeeven more high definition.

Furthermore, FIG. 18C is characterized in that the current supply line4408 and the gate wirings 4403 are formed in parallel, similar to thestructure of FIG. 18B, and in addition, two pixels are formed withlinear symmetry around the current supply line 4408. In addition, it iseffective to form the current supply line 4408 so that it overlaps withone of the gate wirings 4403. In this case, the number of current supplylines can be reduced, and the pixel region can be made even more highdefinition.

By using the structure of the present invention, not only can theconcentration of contaminating impurities within films structuring a TFTbe reduced, but the contaminating impurity concentration in filminterfaces can also be reduced, and therefore fluctuation of TFTcharacteristics can be made smaller and the TFT reliability can beincreased.

What is claimed is:
 1. A display device comprising: a first substratecomprising a transistor, a light-emitting element, and a wiring; asecond substrate over the first substrate; a first sealing materialinterposed between the first substrate and the second substrate, thefirst sealing material being disposed along periphery of the secondsubstrate; and a second sealing material disposed outside the firstsealing material, the second sealing material being in contact with atleast a side surface of the second substrate, wherein the light-emittingelement comprises an organic material, wherein the wiring iselectrically connected to an electrode of the light-emitting element,wherein the wiring comprises a same layer as a source electrode of thetransistor, and wherein the wiring comprises a first region in contactwith the first sealing material.
 2. The display device according toclaim 1, wherein the wiring further comprises a second region in contactwith a conductive material so that the wiring is electrically connectedto a flexible printed circuit.
 3. The display device according to claim1, wherein the transistor comprises a polycrystalline silicon film. 4.The display device according to claim 1, wherein at least one of thefirst sealing material and the second sealing material comprises adrying agent.
 5. The display device according to claim 1, wherein atleast one of the first sealing material and the second sealing materialcomprises barium and oxygen.
 6. The display device according to claim 1,wherein the first sealing material comprises a resin.
 7. The displaydevice according to claim 1, further comprising a filling material,wherein the filling material fills a space surrounded by the firstsubstrate, the second substrate, and the first sealing material.
 8. Thedisplay device according to claim 7, wherein the filling materialcomprises a spacer.
 9. The display device according to claim 7, whereinthe filling material comprises an absorbent material.
 10. A displaydevice comprising: a first substrate comprising: a pixel portioncomprising a light-emitting element over a first transistor with aninsulating film interposed therebetween; and a driver circuit includinga second transistor; a wiring configured to be electrically connected toa flexible printed circuit; a second substrate over the first substrate;a first sealing material interposed between the first substrate and thesecond substrate, the first sealing material being disposed alongperiphery of the second substrate; and a second sealing materialdisposed outside the first sealing material, the second sealing materialbeing in contact with at least a side surface of the second substrate,wherein the wiring is electrically connected to an electrode of thelight-emitting element, wherein the wiring comprises a same layer as asource electrode of the first transistor, and wherein the wiringcomprises a first region in contact with the first sealing material. 11.The display device according to claim 10, wherein the wiring furthercomprises a second region in contact with a conductive material so thatthe wiring is electrically connected to the flexible printed circuit.12. The display device according to claim 10, wherein the insulatinglayer is not in contact with the first sealing material.
 13. The displaydevice according to claim 10, wherein the second transistor comprises apolycrystalline silicon film.
 14. The display device according to claim10, wherein the light-emitting element comprises an organic material.15. The display device according to claim 10, wherein at least one ofthe first sealing material and the second sealing material comprises adrying agent.
 16. The display device according to claim 10, wherein atleast one of the first sealing material and the second sealing materialcomprises barium and oxygen.
 17. The display device according to claim10, wherein the first sealing material comprises a resin.
 18. Thedisplay device according to claim 10, further comprising a fillingmaterial, wherein the filling material fills a space surrounded by thefirst substrate, the second substrate, and the first sealing material.19. The display device according to claim 18, wherein the fillingmaterial comprises a spacer.
 20. The display device according to claim18, wherein the filling material comprises an absorbent material.